1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more specifically, to a method for fabricating a TFT substrate to be used in a display device such as a liquid crystal display device.
2. Description of the Related Art
TFTs (thin film transistors) are used for driving a display device such as a liquid crystal display device.
FIG. 4 shows a partial plan view of a TFT substrate fabricated in accordance with a conventional fabrication method of a semiconductor device. FIGS. 5A to 5J show cross-sectional views each illustrating the process steps in the conventional fabrication method of the semiconductor device of FIG. 4. Among these drawings, FIG. 5J is a cross-sectional view taken along line Xxe2x80x94X in FIG. 4, and FIGS. 5A to 5I show cross-sectional views at the corresponding position in the respective process steps.
As shown in FIGS. 4 and 5J, a TFT substrate 600 used in a liquid crystal display device includes a gate interconnection 63 patterned on a substrate 61, a gate insulating film 62 made of silicon nitride and formed on the entire surface of the substrate 61 so as to cover the gate interconnection 63, an intrinsic semiconductor layer 64 and an n-type semiconductor layer 65 sequentially deposited on the gate insulating film 62 in the shape of islands. The intrinsic semiconductor layer 64 and the n-type semiconductor layer 65 are in particular referred to as a semiconductor layer structure. Furthermore, a base layer 66 and a top layer 67 are provided as source interconnection materials (including a source electrode material and a drain electrode material) on the substrate 61 so as to cover the n-type semiconductor layer 65. The base layer 66 and the top layer 67 are in particular referred to as a metal layer structure.
In the TFT substrate 600, the base layer 66 and the top layer 67 form a source electrode 72, a drain electrode 73 and a source interconnection 74. A gap portion 71 for the transistor (hereinafter, referred to as xe2x80x9ca transistor gap portionxe2x80x9d) is formed between the source electrode 72 and the drain electrode 73 so as to run through the top layer 67, the base layer 66 and the n-type semiconductor layer 65 and into the intrinsic semiconductor layer 64.
In the TFT substrate 600, ITO is used as a material of the base layer 66 of a source interconnection material. In the step of dry etching the top layer 67, the base layer 66 of ITO is not etched. Therefore, the etching is performed without affecting the underneath portion already formed below the ITO film 66 since the ITO film 66 functions as a barrier. Thus, the patterning of the source interconnection is commonly done by separately performing etching of the top layer 67 on the ITO film 66, etching of the ITO film 66, and etching of the n-type semiconductor layer 65 and the intrinsic semiconductor layer 64 to form the transistor gap portion 71.
Hereinafter, as a conventional fabrication method of the TFT substrate, a method of forming a source electrode, a drain electrode, a source interconnection (hereinafter, these are collectively referred to as xe2x80x9ca source interconnection and the likexe2x80x9d), and a transistor gap portion will be described with reference to FIGS. 5A to 5J.
As shown in FIG. 5A, the gate interconnection 63 is patterned in a predetermined pattern on the substrate 61, and the gate insulating film 62 is formed thereon. Then, the semiconductor layer structure including the intrinsic semiconductor layer 64 of amorphous silicon and the n-type semiconductor layer 65 of N+ amorphous silicon are formed on the gate insulating film 62 in the shape of an island.
Next, as shown in FIG. 5B, the ITO film (base layer) 66 is formed on the resultant structure of FIG. 5A by sputtering or the like. Thereafter, the top layer 67 of a source interconnection material is formed on the resultant structure by sputtering or the like, as shown in FIG. 5C.
Next, a resist layer is provided on the top layer 67 by a spin coat method, or the like. The resist layer is then patterned by photolithography to form a first photoresist pattern 68, as shown in FIG. 5D.
Next, as shown in FIG. 5E, portions of the top layer 67 not covered by the first photoresist pattern 68 are removed by a chemical liquid treatment or dry etching. In this step, the first photoresist pattern 68 functions as a mask, so that the other portions of the top layer 67 covered with the first photoresist pattern 68 are unremoved. Furthermore, the entire underlying ITO film 66 is not substantially etched away because an etching select ion ratio thereof with respect to the top layer 67 is infinite. It should be noted that when the etching (patterning) of the top layer 67 is performed by dry etching in this step, etching residues (not shown) from the top layer 67 remain.
Next, as shown in FIG. 5F, the first photoresist pattern 68 is removed by a chemical liquid treatment. When the top layer 67 has been dry etched to be patterned in the previous step, the aforementioned etching residues are also removed by this chemical liquid treatment.
Next, another resist layer is provided on the patterned top layer 67 by a spin coat method or the like, and then patterned by a photolithography method so as to form a second photoresist pattern 69, as shown in FIG. 5G.
Next, as shown in FIG. 5H, portions of the ITO film 66 not covered by the second photoresist pattern 69 are removed by a chemical liquid treatment or dry etching. During this step, the second photoresist pattern 69 functions as a mask, so that the other portions of the ITO film 66 covered by the second photoresist pattern 69 are not removed. It should be noted that when the ITO film 66 is removed by dry etching in this step, etching residues (not shown) from the ITO film 66 are left on the n-type semiconductor layer 65.
Next, as shown in FIG. 5I, the second photoresist pattern 69 is removed by a chemical liquid treatment. When the ITO film 66 has been etched by dry etching to be patterned in the preceding step, the aforementioned etching residues are also removed by this chemical liquid treatment. Thus, a source interconnection and the like are formed.
Next, a portion of the N+ amorphous silicon layer 65 is removed by dry etching. Furthermore, the amorphous silicon layer 64 is partly removed by dry etching at a position corresponding to the removed portion of the N+ silicon layer 65. Finally, residues or the like generated during the above dry etching steps are removed by a chemical liquid treatment, thereby forming the transistor gap portion 71, as shown in FIG. 5J.
Thus, the TFT substrate 600 is fabricated.
In the above described conventional method for fabricating a TFT substrate, an ITO film is used for a base layer to be a source interconnection and the like. A top layer, which is to be a source interconnection and the like, is made of a metal material such as aluminum, an aluminum alloy, titanium, titanium compound including titanium nitride, chromium, tungsten, and a mixture thereof. An etchant for etching the top layer is selected in accordance with a material for the top layer. For example, when a material for the top layer is one of an aluminum-group material, a molybdenum-group material, and a tungsten-group material, a mixture of phosphoric acid, acetic acid and nitric acid, or the like is used. When a material for the top layer is a titanium-group material, hydrofluoric acid or the like is used. When a material for the top layer is a tantalum-group material, a mixture of hydrofluoric acid and nitric acid is used. Furthermore, a photoresist pattern functioning as a mask is made of a resin or the like.
In the step of etching the top layer made of the aforementioned material and provided above the ITO film, the portion of the underlying layered structure disposed below the ITO film is advantageously prevented from being etched because the etching selection ratio of the ITO film with respect to the top layer is infinite. However, as described above, it is necessary in the conventional art to separately perform etching of the top layer, etching of the base layer made of the ITO film, and etching of the transistor gap portion. These etching steps are accompanied by a number of photolithography steps. Therefore, there is a problem that many masks and process steps are required to be employed for the fabrication process.
It is preferable to perform the respective etching steps of the top layer, the base layer made of the ITO film, and the transistor gap portion by dry etching rather than a chemical liquid treatment in order to reduce the space required for the fabrication and simplify the fabrication process. Furthermore, dry etching is suitable for the subsequent etching to be performed for obtaining a very fine pattern.
Furthermore, in the aforementioned conventional fabrication method of the TFT substrate, the steps of removing the first photoresist pattern 68 and the second photoresist pattern 69 by a chemical liquid treatment are required as de scribed with reference to FIGS. 5A to 5J. One of the purposes of these steps is to remove the etching residues generated by the preceding dry etching.
Hereinafter, a case where the step of removing the second photoresist pattern 69 is omitted from the aforementioned fabrication process for the TFT substrate 600 for the purpose of reducing the number of fabrication steps will be described with reference to FIGS. 6A to 6C. Like components are designated by like reference numerals in FIGS. 5A to 5J and in FIGS. 6A to 6C, and the descriptions therefor will be omitted below.
The same fabrication steps as described with reference to FIGS. 5A to 5G are first performed. After these steps, as shown in FIG. 6A, portions of the ITO film 66 not covered by the second photoresist pattern 69 are etched away by dry etching. In this step, etching residues 70 from an ITO film 66 are left on the N+ amorphous silicon layer 65.
When the transistor gap portion 71 (see FIG. 6C) is successively formed by etching after the etching of the ITO film 66 in the same chamber without removing the second photoresist pattern 69 and the etching residues 70 by a chemical liquid treatment, portions of the N+ amorphous silicon layer 65 and the amorphous silicon layer 64 are left unetched to be in a pillar-like pattern corresponding to the positions of the etching residues 70, as seen in FIG. 6B. This is because the etching residues 70 function as a mask, thereby hindering the etching of the N+ amorphous silicon layer 65 and the amorphous silicon layer 64.
Finally, the etching residues 70 and the second photoresist pattern 69 are removed by a chemical liquid treatment, thereby forming a transistor gap portion 71, as shown in FIG. 6C.
As described hereinbefore, the TFT substrate 600xe2x80x2 is fabricated.
The portions of the semiconductor layer structure (including the N+ amorphous silicon layer 65 and the amorphous silicon layer 64) which are left unetched to be in a pillar-like shape in the transistor gap portion 71 may cause a surface leakage current between the source electrode 72 and the drain electrode 73. Due to the surface leakage current, it is not possible to sufficiently reduce the OFF current of the transistor.
Furthermore, even in the case where the semiconductor layer structure is not left to be in a pillar-like shape (i.e., when any unetched portions of the semiconductor layer structure, if they exist, are undetectable at an SEM level) after the etching for forming the transistor gap portion 71, a minute amount of residue present in the transistor gap portion 71 causes undesirable electrical connections to be established by a later thermal aging process, whereby the OFF current of the resultant transistor increases gradually.
Thus, there is a need to etch away an area to be a transistor gap portion between a source electrode and a drain electrode such that substantially no residue remains. To this end, it is necessary to remove the residues after the etching of the base layer and before the etching of the transistor gap portion. Therefore, in order to realize such a purpose, a step of removing the etching residues by a chemical liquid treatment without deteriorating the TFT characteristics is essential in the conventional art.
According to the present invention, a method for fabricating a semiconductor device including a semiconductor layer structure, a source electrode and a drain electrode formed on the semiconductor layer structure, and a source interconnection connected to the source electrode is provided. The method includes the steps of: (a) forming the semiconductor layer structure on a substrate; (b) forming a metal layer structure so as to cover the semiconductor layer structure; (c) forming a resist layer having a predetermined pattern on the metal layer structure; (d) performing a first etching process for the metal layer structure using the resist layer as a mask so as to form the source electrode, the drain electrode and the source interconnection; and (e) performing a second etching process for the semiconductor layer structure using the resist layer as a mask so as to form a transistor gap portion between the source electrode and the drain electrode. The respective first and second etching processes in the steps (d) and (e) are performed using the same resist layer as the mask in the same chamber.
In one embodiment, the resist layer is a photoresist layer, and the respective first and second etching processes in the steps (d) and (e) are successively performed using the same resist layer as the mask in the same chamber by reactive ion etching.
The first etching process for the metal layer structure in the steps (d) may be performed under a gas pressure of about 10 mTorr or less.
The method may further include, between the steps (d) and (e), a step (f) of performing a middle treatment process in which the substrate is subjected to reactive ion etching with a mixed gas of CF4 and O2 using the resist layer as a mask in the same chamber.
The method may further include, after the step (e), a step (g) of performing a damage treatment process in which the substrate is subjected to plasma etching using the resist layer as a mask.
In one embodiment, the metal layer structure contains Ti: and the first etching process for the metal layer structure in the step (d) is performed with a mixed gas of Cl2 and BCl3.
In one embodiment, the second etching process for the semiconductor layer structure in the step (e) is performed with a Cl2 gas.
The method may further include, between the steps (e) and (g), a step (h) of performing an after-treatment process in which the substrate is subjected to reactive ion etching with a mixed gas of CF4 and O2 using the resist layer as a mask in the same chamber.
Hereinafter, the function of the present invention will be described.
In the method for fabricating a semiconductor device of the present invention, the etching is performed through the metal layer structure so as to reach the inside of the semiconductor layer structure with the same etching pattern. Therefore, a source electrode, a drain electrode, a source interconnection and a transistor gap portion can be formed with a single etching pattern (mask). Accordingly, the smaller number of photolithography steps is to be performed, thereby simplifying the fabrication process.
According to a preferred embodiment of the present invention, the respective dry etching steps by reactive ion etching for the metal layer structure and the semiconductor layer structure are successively performed in the same chamber. Thus, a method for forming the source electrode, the drain electrode, the source interconnection and the transistor gap portion can be performed in a smaller space and with a reduced number of steps.
According to a preferred embodiment of the present invention, a step of performing a middle treatment, in which a substrate is subjected to reactive ion etching, is performed between a step of etching the metal layer structure and a step of etching the semiconductor layer structure. Thus, the etching residues from the metal layer structure can be removed, and as a result, the formation of pillar-like semiconductor portions in an area to be the transistor gap portion can be prevented. Accordingly, a surface leakage current is prevented from increasing, so that desirable TFT characteristics can be maintained.
According to a preferred embodiment of the present invention, a step of performing a damage treatment, in which the substrate is subjected to plasma etching, is further performed after the step of etching the semiconductor layer structure. Thereby, a damaged layer at the transistor gap portion generated by reactive ion etching can be removed, and as a result, damages of the transistor gap portion can be reduced. Thus, TFT characteristics can be improved.
According to a preferred embodiment of the present invention, a step of performing an after-treatment for the substrate, in which the substrate is subjected to reactive ion etching with a mixed gas of CF4 and O2, is further performed after the step of etching the semiconductor layer structure. Thus, chlorine remaining on the substrate can be removed by the CF4 gas, and a resist layer can be ashed with the O2 gas.
Thus, the invention described herein makes possible the advantages of providing a method for fabricating a semiconductor device in which a fabrication process is shortened without deteriorating the TFT characteristics.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.